JP-A-2002-340853 discloses a device having the configuration shown in FIG. 1A as a semiconductor device for correcting variation in various electrical properties as described above. The device shown in FIG. 1A is provided with: sensor 3001, pseudo-resistor (R) 3002 and amplifier 3005 that are connected to sensor 3001, and switches 3003, 3004 connected in a series to sensor 3001 and pseudo-resistor 3002, respectively. Normally, switch 3003 connected in a series to sensor 3001 is ON, and switch 3004 on the side of pseudo-resistor 3002 is OFF, whereby only sensor 3001 is connected to amplifier 3005 and the signal of sensor 3001 is read by amplifier 3005. When performing correction, however, only switch 3004 on the pseudo-resistor 3002 side is ON, whereby the signal level of pseudo-resistor 3002 is read by way of amplifier 3005. Analog-to-digital converter (ADC) 3006 is connected in the stage following amplifier 3005, and ADC 3006 converts the output of amplifier 3005 to a digital signal. The correction of variation is realized by comparing the digitized sensor signal with the digitized pseudo-resistor signal.
JP-A-5-087936 discloses a configuration provided with a plurality of sensors 3010 along with switches 3011 connected in a series to each of these sensors 3010 and a single amplifier 3012 that is connected in common to sensors 3010. Amplifiers typically have variations in offset voltage, but in the example shown in FIG. 1B, instead of providing a plurality of amplifiers for the plurality of sensors 3010, the signals from the plurality of sensors 3010 are amplified by one amplifier 3012 while switching by means of switches 3011, whereby the contribution due to the offset voltage of amplifier 3012 is prevented from varying among the plurality of sensors 3011.
JP-A-3-235293 discloses an example that corrects variation in a semiconductor memory. The configuration disclosed in JP-A-3-235293 is provided with: a plurality of memory cells, switches connected to these memory cells, a bus for connecting together this plurality of switches, a reference circuit connected to the bus, and a sense-amplifier. The signal read-out from the memory cells is normally carried out with only the switch of a particular memory cell turned ON, the signal of this memory cell then appearing in the bus. The sense-amplifier connected to the bus amplifies and reads out this signal. On the other hand, the reference circuit is itself also provided with a switch, this switch being OFF during normal read-out. However, during correction of variation, only the switch of the reference circuit is ON, and only current of the reference circuit flows to the bus to be amplified by the sense-amplifier and then read out. Comparison of this signal from the reference circuit and the signals from the memory cells enables detection of the variation of each memory cell signal from the reference circuit signal.
As shown in FIG. 1C, the example shown in JP-A-7-202961 is provided with: mixer (MOD) 3015 supplied with local signal (LO), detection circuit (DC DET) for reading the dc voltage of the output of the mixer, and circuit (OFS. Cal.) 3017 for, according to the output of detection circuit 3016, adjusting the dc voltage of the baseband signal supplied from baseband circuit (BB Gen.) 3019. In addition, the circuit shown in FIG. 1C is further provided with circuit (OFS. Cal.) 3018 that works upon the dc voltage setting function of mixer 3015 itself. Local leakage (also called “carrier leakage”) of the mixer is represented by the dc offset, and the local leakage can be reduced by measuring the dc offset and then compensating the offset.
As shown in FIG. 1D, the example shown in JP-A-2004-020325 is provided with: sensor 3021, a plurality of read-out circuits 3022 that read the data from the sensor, multilevel voltage generator (MLVG) 3023 for correcting the variation of the sensor, analog bus 3024 for distributing the multilevel voltages from multilevel voltage generator 3023 to all read-out circuits 3022, wiring 3025 for collecting at one point the signals from read-out circuits 3022, and amplifier 3026 connected to wiring 3025 for extracting a signal outside the chip. Multiplexers for extracting necessary voltage from analog bus 3025 are arranged in read-out circuits 3022, and adjustment is realized by changing the voltage extracted from analog bus 3025 according to variation of sensor 3021 such that read-out circuits 3022 are not saturated despite variation in sensor 3012. A multiplexer is also arranged at the output of each read-out circuit 3022, and by successively selecting read-out circuits 3022 from which signals are sent to wiring 3025, sensor signals from all read-out circuits 3022 can be read outside the chip.
Still further, examples have been reported in which an envelope detector for measuring local leakage or I/Q mismatching is provided in the stage following a mixer, the envelope detector output is converted to a digital signal by means of an ADC, and the transmission baseband signal is intentionally altered digitally such that local leakage or I/Q mismatching is reduced (I. Vassiliou et al., A single-chip digitally calibrated 5.15-5.825-GHz 0.18-um CMOS transceiver for 802.11a wireless LAN, IEEE JSSC, Vol. 38, No. 12, 2003, pages 2221-2231).
In recent years, wideband communication has become necessary in wireless communication, and wideband communication of 54 Mbps has been put to practical use in, for example, IEEE 802.11a standards. Further, in recent years, standards have been drawn up for ultra-wideband (UWB), which is wireless communication of the 1-Gbps class in the IEEE 802.15 TG3a standards for wireless close-range communications. In wireless communication of this type, the occupied frequency bandwidth becomes extremely broad based on Shannon's law, for example, a wide bandwidth spanning 3.1 GHz to 10.6 GHz being used in UWB (for example, refer to Nikkei Electronics, Mar. 31, 2003 issue, pp. 30 to 31). Wideband wireless communication that spans three times the frequency ratio, i.e., frequencies of approximately three times the minimum frequency, is still unavailable.
For example, in a UWB wireless system referred to as the “multiband system,” a frequency region ranging from 3.1 GHz to 10.6 GHz is divided into, for example, fourteen sub-bands #1 to #14 each corresponding to a channel, as shown in FIG. 2. Each of the fourteen sub-bands has a bandwidth of approximately 500 MHz, and the multi-band UWB wireless system is formed such that a wide bandwidth is covered by successive high-speed hopping between the sub-bands.
The documents cited in the present specification are listed below:
Patent Document 1: JP-A-2002-340853;
Patent Document 2: JP-A-H05-087936;
Patent Document 3: JP-A-H03-235293;
Patent Document 4: JP-A-H07-202961;
Patent Document 5: JP-A-2004-020325;
Non-Patent Document 1: I. Vassiliou et al., A single-chip digitally calibrated 5.15-5.825-GHz 0.18-um CMOS transceiver for 802.11a wireless LAN, IEEE JSSC, Vol. 38, No. 12, 2003, pages 2221-2231;
Non-Patent Document 2: Nikkei Electronics, Mar. 31, 2003 issue, pp. 30-31.